NXP Semiconductors /LPC43xx /SCT /DMAREQ1

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Interpret as DMAREQ1

Description

SCT DMA request 1 register

Fields

DEV_10	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_11	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_12	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_13	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_14	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_15	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_16	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_17	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_18	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_19	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_110	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_111	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_112	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_113	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_114	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
DEV_115	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
RESERVED	Reserved
DRL1	A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
DRQ1	This read-only bit indicates the state of DMA Request 1.

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